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Research Project: Synthesizer: Low noise fully integrated CMOS tuning systems for digital transmission systems
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2009

Nauta, B. and van de Beek, R.C.H. and Vaucher, C.S. (2009) Phase-Locked-loop with reduced clock jitter. Patent US7606343B2 (Assigned).

2007

van de Beek, R.C.H. and Klumperink, E.A.M. and Nauta, B. and Vaucher, C.S. (2007) Phase locked loop. Patent US7218157 (Assigned).

2005

van de Beek, R.C.H. and Klumperink, E.A.M. and Nauta, B. and Vaucher, C.S. (2005) Phase locked loop. Patent US20050525862 (Application).