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Research Project: Innovative CT: Innovative clocking devices
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2015

Gao, Xiang and Klumperink, E.A.M. and Nauta, B. (2015) Sub-sampling PLL techniques. (Invited) In: IEEE Custom Integrated Circuits Conference, CICC 2015, 28-30 Sept 2015, San Jose, CA, USA. pp. 1-8. IEEE. ISBN 978-1-4799-8681-1

2013

Gao, Xiang and Bahai, A. and Bohsali, M. and Djabbari, A. and Klumperink, E.A.M. and Nauta, B. and Socci, G. (2013) Spur reduction technique for sampling PLLs. Patent US8373481 (Assigned).
Gao, Xiang and Bahai, A. and Bohsali, M. and Djabbari, A. and Klumperink, E.A.M. and Nauta, B. and Socci, G. (2013) Low power and low spur sampling PLL. Patent US8395427 (Assigned).
Gao, Xiang and Bahai, A. and Bohsali, M. and Djabbari, A. and Klumperink, E.A.M. and Nauta, B. and Socci, G. (2013) Sampling phase lock loop (PLL) with low power clock buffer. Patent US8427209 (Assigned).

2012

Gao, Xiang and Bahai, A. and Bohsali, M. and Djabbari, A. and Klumperink, E.A.M. and Nauta, B. and Socci, G. (2012) Sampling phase lock loop (PLL) with low power clock buffer. Patent US201213654051 (Application).

2010

Dutta, R. and Bhattacharyya, T.K. and Gao, Xiang and Klumperink, E.A.M. (2010) Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. In: 23th International Conference on VLSI Design, VLSID 2010, 3-7 Jan 2010, Bangalore, India. pp. 152-157. IEEE Press. ISSN 1063-9667 ISBN 978-1-4244-5541-6
Gao, Xiang (2010) Low jitter low power phase locked loops using sub-sampling phase detection. PhD thesis, University of Twente. ISBN 978-90-365-3022-4
Gao, Xiang and Bahai, A. and Bohsali, M. and Djabbari, A. and Klumperink, E.A.M. and Nauta, B. and Socci, G. (2010) Low power and low spur sampling PLL. Patent US20100973323 (Application).
Gao, Xiang and Bahai, A. and Bohsali, M. and Djabbari, A. and Klumperink, E.A.M. and Nauta, B. and Socci, G. (2010) Spur reduction technique for sampling PLLs. Patent US20100973353 (Application).
Gao, Xiang and Klumperink, E.A.M. and Nauta, B. and Bohsali, M. and Kiaei, A. and Socci, G. and Djabbari, A. (2010) Phase-locked loop including sampling phase detector and charge pump with pulse width control. Patent US7737743 (Assigned).
Gao, Xiang and Klumperink, E.A.M. and Socci, G. and Bohsali, M. and Nauta, B. (2010) Spur-reduction techniques for PLLs using sub-sampling phase detection. In: Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International, 7-11 Feb 2010, San Francisco. pp. 474-475. IEEE Press. ISSN 0193-6530 ISBN 978-1-4244-6033-5
Gao, Xiang and Klumperink, E.A.M. and Socci, G. and Bohsali, M. and Nauta, B. (2010) Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector. IEEE journal of solid-state circuits, 45 (9). pp. 1809-1821. ISSN 0018-9200 *** ISI Impact 3,299 ***
Gao, Xiang and Klumperink, E.A.M. and Socci, G. and Bohsali, M. and Nauta, B. (2010) A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power. In: IEEE Symposium on VLSI Circuits, VLSI 2010, 16-18 June 2010, Hawai, Honolulu. pp. 139-140. IEEE Press. ISBN 978-1-4244-5454-9

2009

Gao, Xiang and Klumperink, E.A.M. and Bohsali, M. and Nauta, B. (2009) A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS. In: IEEE International Solid-State Circuits Conference, 8-12 February 2009, San Francisco. pp. 392-393. IEEE Computer Society. ISBN 978-1-4244-3458-9
Gao, Xiang and Klumperink, E.A.M. and Bohsali, M. and Nauta, B. (2009) A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD/CP Noise Is not multiplied by N2 IEEE journal of solid-state circuits, 44 (12). pp. 3253-3263. ISSN 0018-9200 *** ISI Impact 3,299 ***
Gao, Xiang and Klumperink, E.A.M. and Boshali, M. and Nauta, B. (2009) A PLL Exploiting Sub-Sampling of the VCO Output to Reduce In-band Phase Noise. In: Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing, 26-27 nov 2009, Veldhoven, the Netherlands. pp. 326-329. Technology Foundation STW. ISBN 978-90-73461-62-8
Gao, Xiang and Klumperink, E.A.M. and Geraedts, P.F.J. and Nauta, B. (2009) Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops. IEEE Transactions on Circuits and Systems II: Express Briefs, 56 (2). pp. 117-121. ISSN 1549-7747 *** ISI Impact 1,136 ***
Klumperink, E.A.M. and Gao, Xiang and Nauta, B. (2009) Polyphase Multipath Circuits for Cognitive Radio and Flexible Multi-phase Clock Generation. In: Circuits and Systems for Future Generations of Wireless Communications. Integrated Circuits and Systems. Springer Netherlands, pp. 145-168. ISBN 978-1-4020-9917-5

2008

Gao, Xiang and Klumperink, E.A.M. and Nauta, B. (2008) Advantages of Shift Registers over DLLs for Flexible Low Jitter Multiphase Clock Generation. IEEE transactions on circuits and systems II: Express Briefs, 55 (3). pp. 244-248. ISSN 1549-7747 *** ISI Impact 1,136 ***
Gao, Xiang and Klumperink, E.A.M. and Nauta, B. and Bohsali, M. and Kiaei, A. and Socci, G. and Djabbari, A. (2008) Phase-locked loop including sampling phase detector and charge pump with pulse width control. Patent US20080044522 (Application).

2007

Gao, Xiang and Klumperink, E.A.M. and Nauta, B. (2007) Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. In: Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), 27-30 May 2007, New Orleans, USA. pp. 2854-2857. IEEE Press. ISBN 1-4244-0921-7