EEMCS

Gao, X. and Klumperink, E.A.M. and Nauta, B. and Bohsali, M. and Kiaei, A. and Socci, G. and Djabbari, A. (2010) Phase-locked loop including sampling phase detector and charge pump with pulse width control. Patent US7737743 (Assigned).

Gao, X. and Klumperink, E.A.M. and Nauta, B. and Bohsali, M. and Socci, G. and Djabbari, A. (2010) Low power and low spur sampling PLL. Patent US20100973323 (Application).

Gao, X. and Klumperink, E.A.M. and Nauta, B. and Bohsali, M. and Socci, G. and Djabbari, A. (2010) Spur reduction technique for sampling PLLs. Patent US20100973353 (Application).

Gao, X. and Klumperink, E.A.M. and Socci, G. and Bohsali, M. and Nauta, B. (2010) Spur-reduction techniques for PLLs using sub-sampling phase detection. In: Solid-State Circuits Conference Digest of Technical Papers (ISSCC) 2010 IEEE International, 7-11 Feb 2010, San Francisco. pp. 474-475. IEEE Press. ISSN 0193-6530 ISBN 978-1-4244-6033-5

Gao, X. and Klumperink, E.A.M. and Socci, G. and Bohsali, M. and Nauta, B. (2010) Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector. IEEE journal of solid-state circuits, 45 (9). pp. 1809-1821. ISSN 0018-9200 *** ISI Impact 3,127 ***

Gao, X. and Klumperink, E.A.M. and Socci, G. and Bohsali, M. and Nauta, B. (2010) A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power. In: IEEE Symposium on VLSI Circuits, VLSI 2010, 16-18 June 2010, Hawai, Honolulu. pp. 139-140. IEEE Press. ISBN 978-1-4244-5454-9

Gao, X. and Klumperink, E.A.M. and Bohsali, M. and Nauta, B. (2009) A 2.2GHz 7.6mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18μm CMOS. In: IEEE International Solid-State Circuits Conference, 8-12 February 2009, San Francisco. pp. 392-393. IEEE Computer Society. ISBN 978-1-4244-3458-9

Gao, X. and Klumperink, E.A.M. and Bohsali, M. and Nauta, B. (2009) A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD/CP Noise Is not multiplied by N² IEEE journal of solid-state circuits, 44 (12). pp. 3253-3263. ISSN 0018-9200 *** ISI Impact 3,127 ***

Gao, X. and Klumperink, E.A.M. and Nauta, B. and Bohsali, M. and Kiaei, A. and Socci, G. and Djabbari, A. (2008) Phase-locked loop including sampling phase detector and charge pump with pulse width control. Patent US20080044522 (Application).