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957 Scheduling and Allocation of Non-Manifest Loops on Hardware Graph-Models
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Mansour, O. and Etalle, S. and Krol, T. (2001) Scheduling and Allocation of Non-Manifest Loops on Hardware Graph-Models. In: 2nd PROGRESS workshop on Embedded Systems, 18 Oct 2001, Veldhoven, The Netherlands. pp. 153-160. Technology Foundation STW. ISBN 90-73461-26-X

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Abstract

We address the problem of scheduling non-manifest data dependant periodic loops for high throughput DSP-applications based on a streaming data model. In contrast to manifest loops, non-manifest data dependant loops are loops where the number of iterations needed in order to perform a calculation is data dependant and hence not known at compile time. For the case of manifest loops, static scheduling techniques have been devised which produce near optimal schedules. Due to the lack of exact run-time execution knowledge of non-manifest loops, these static scheduling techniques are not suitable for tackling scheduling problems of DSP-algorithms with non-manifest loops embedded in them. We consider the case where (a) a-priori knowledge of the data distribution, and (b) worst case execution time of the non-manifest loop are known and a constraint on the total execution time has been given. Under these conditions dynamic schedules of the non-manifest data dependant loops within the DSP-algorithm are possible. We show how to construct hardware which dynamically schedules these non-manifest loops. The sliding window execution, which is the execution of a non-manifest loop when the data streams through it, of the constructed hardware will guarantee real time performance for the worst case situation. This is the situation when each non-manifest loop requires its maximum number of iterations.

Item Type:Conference or Workshop Paper (Full Paper, Poster)
Research Group:EWI-DIES: Distributed and Embedded Security, EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-UBRICKS: Building Blocks for Ubiquitous Computing and Communication
Research Project:High2: High-level synthesis tools for high-throughput digital systems applications
Additional Information:Imported from DIES
ID Code:957
Status:Published
Deposited On:12 December 2005
Refereed:No
International:No
More Information:statistics

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