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896 Max-Log-MAP Mapping on an FPFA
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Heysters, P.M. and Smit, L.T. and Smit, G.J.M. and Havinga, P.J.M. (2002) Max-Log-MAP Mapping on an FPFA. In: IInternational Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002, Las Vegas, Nevada. pp. 90-96. CSREA Press. ISBN 1-892512-96-3

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Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.

Item Type:Conference or Workshop Paper (Proceedings UNSPECIFIED, Presentation Type UNSPECIFIED)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-UBRICKS: Building Blocks for Ubiquitous Computing and Communication
Additional Information:Imported from DIES
ID Code:896
Deposited On:12 December 2005
More Information:statistics

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