EEMCS EPrints Service

Education

Research

Prospective Students

Jobs

Publications

Intranet (internal)

Nederlands

Contact

Organisation

776 Two Architectures for On-chip Virtual Channel Router

Home Policy Brochure Browse Search User Area Contact Help

Kavaldjiev, N.K. and Smit, G.J.M. and Jansen, P.G. (2004) Two Architectures for On-chip Virtual Channel Router. In: 5th PROGRESS Symposium on Embedded Systems, Nieuwegein, The Netherlands. pp. 90-95. Technology Foundation STW. ISBN 90-73461-41-3

Full text available as:

PDF

41 Kb

Abstract

This paper compares the implementation results of two architectures for virtual channel router. Since the router is used for building an on-chip network, its small size is critical. Together with the total design area we provide information about the distribution of this area between the main router blocks and thus give insight about the cost of each block. The comparison shows that one of the architectures results in smaller implementation area and overcomes some performance problems presented by the other architecture.

Item Type:	Conference or Workshop Paper (Proceedings UNSPECIFIED, Presentation Type UNSPECIFIED)
Research Group:	EWI-DIES: Distributed and Embedded Security, EWI-CAES: Computer Architecture for Embedded Systems
Research Program:	CTIT-UBRICKS: Building Blocks for Ubiquitous Computing and Communication
Research Project:	Gecko: Communication and Scheduling in Reconfigurable Multimedia
Additional Information:	Imported from DIES
ID Code:	776
Status:	Published
Deposited On:	12 December 2005
Refereed:	No
International:	No
More Information:	statistics

Export this item as:

To correct this item please ask your editor

Repository Staff Only: edit this item