EEMCS EPrints Service
Kavaldjiev, N.K. and Smit, G.J.M. and Jansen, P.G. (2004) Two Architectures for On-chip Virtual Channel Router. In: 5th PROGRESS Symposium on Embedded Systems, Nieuwegein, The Netherlands. pp. 90-95. Technology Foundation STW. ISBN 90-73461-41-3
Full text available as:
This paper compares the implementation results of two architectures for virtual channel router. Since the router is used for building an on-chip network, its small size is critical. Together with the total design area we provide information about the distribution of this area between the main router blocks and thus give insight about the cost of each block. The comparison shows that one of the architectures results in smaller implementation area and overcomes some performance problems presented by the other architecture.
Export this item as:
To correct this item please ask your editor
Repository Staff Only: edit this item