EEMCS

Home > Publications
Home University of Twente
Education
Research
Prospective Students
Jobs
Publications
Intranet (internal)
 
 Nederlands
 Contact
 Search
 Organisation

EEMCS EPrints Service


27826 Partial-Order Reduction for GPU Model Checking
Home Policy Brochure Browse Search User Area Contact Help

Neele, T. and Wijs, A. and Bosnacki, D. and van de Pol, J.C. (2016) Partial-Order Reduction for GPU Model Checking. In: Proceedings of the 14th International Symposium on Automated Technology for Verification and Analysis, ATVA 2016, 17-20 Oct 2016, Chiba, Japan. pp. 357-374. Lecture Notes in Computer Science 9938. Springer Verlag. ISSN 0302-9743 ISBN 978-3-319-46519-7

Full text available as:

PDF (Publisher's version)

441 Kb
PDF (Author's version)

309 Kb

Official URL: http://dx.doi.org/10.1007/978-3-319-46520-3_23

Abstract

Model checking using GPUs has seen increased popularity over the last years. Because GPUs have a limited amount of memory, only small to medium-sized systems can be verified. For on-the-fly explicit-state model checking, we improve memory efficiency by applying partial-order reduction. We propose novel parallel algorithms for three practical approaches to partial-order reduction. Correctness of the algorithms is proved using a new, weaker version of the cycle proviso. Benchmarks show that our implementation achieves a reduction similar to or better than the state-of-the-art techniques for CPUs, while the amount of runtime overhead is acceptable.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-FMT: Formal Methods and Tools
Research Program:CTIT-General
Research Project:3TU.BSR: Big Software on the Run
ID Code:27826
Status:Published
Deposited On:20 April 2017
Refereed:Yes
International:Yes
More Information:statistics

Export this item as:

To correct this item please ask your editor

Repository Staff Only: edit this item