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Neele, T. and Wijs, A. and Bosnacki, D. and van de Pol, J.C. (2016) Partial-Order Reduction for GPU Model Checking. In: Proceedings of the 14th International Symposium on Automated Technology for Verification and Analysis, ATVA 2016, 17-20 Oct 2016, Chiba, Japan. pp. 357-374. Lecture Notes in Computer Science 9938. Springer Verlag. ISSN 0302-9743 ISBN 978-3-319-46519-7
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Official URL: http://dx.doi.org/10.1007/978-3-319-46520-3_23
Model checking using GPUs has seen increased popularity over the last years. Because GPUs have a limited amount of memory, only small to medium-sized systems can be verified. For on-the-fly explicit-state model checking, we improve memory efficiency by applying partial-order reduction. We propose novel parallel algorithms for three practical approaches to partial-order reduction. Correctness of the algorithms is proved using a new, weaker version of the cycle proviso. Benchmarks show that our implementation achieves a reduction similar to or better than the state-of-the-art techniques for CPUs, while the amount of runtime overhead is acceptable.
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