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27352 Efficient Utilization of Hierarchical iJTAG Networks for Interrupts Management
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Ibrahim, A.M.Y. and Kerkhoff, H.G. (2016) Efficient Utilization of Hierarchical iJTAG Networks for Interrupts Management. In: 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 19-20 Sept 2016, Storrs, CT, USA. pp. 97-102. IEEE Computer Society. ISBN 978-1-5090-3623-3

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Official URL: http://dx.doi.org/10.1109/DFT.2016.7684077

Abstract

Modern systems-on-chips rely on embedded instruments for testing and debugging, the same instruments could be used for managing the lifetime dependability of the chips. The IEEE 1687 (iJTAG) standard introduces an access network to the instruments based on reconfigurable scan paths. During lifetime, instruments could be required to initiate communication with a system-level dependability manager for different reasons. For example, fault/event occurrences or measurement read-out requests; however iJTAG networks are inherently master/slave networks, where the instruments are the network slaves. In this work, a scalable interrupts-management methodology is presented for allowing instruments-initiated communication using hierarchical iJTAG networks. The presented method allows for an efficient access of the network according to the required use-case by allowing the network to be configured into a corresponding optimized mode. In addition, a novel on-chip localization methodology is presented, which significantly reduces the localization time of interrupting instruments as compared to previous works.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-General
Research Project:ELESIS: European Library Based Flow Of Embedded Silicon Test Instruments
ID Code:27352
Status:Published
Deposited On:04 November 2016
Refereed:Yes
International:Yes
More Information:statistics

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