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Dutta, R. (2016) Ultra low power and interference robust transceiver techniques for wireless sensor networks. PhD thesis, Univ. of Twente. CTIT Ph.D. thesis series No 16-399 ISBN 978-90-365-4166-4
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Official URL: http://dx.doi.org/10.3990/1.9789036541664
Wireless sensor networks (WSNs) have the potential to build breakthrough technologies for a variety of applications to improve human life. Some of the important applications are prevention, prediction and rescue of disasters, medical study and cure, improve the energy efficiency of homes and industries and study environments in remote places. These applications desire an ultra low power sensor node to extend the battery life, so that minimum or zero maintenance is required after initial installation. With the advancement of CMOS technology, power consumption of processors and semiconductor memories has reduced drastically. However, the radio transceiver power consumption has not experienced much power reduction because of its RF analog circuits. This makes the transceiver the bottleneck with respect to lifetime in existing sensor nodes. Another growing challenge for the sensor node transceiver is its interference robustness. Therefore there is a need of ultra low energy and interference robust wireless transceivers to enable WSNs to thrive in several applications which are not yet successful.This thesis targets an energy optimized and interference-robust radio communication system for WSNs. Special focus is given to the receiver, as the receiver is either always ON or ON for more time than the transmitter for duty-cycled radio and hence it is the critical part of the transceiver performance both in terms of power reduction and interference mitigation. A system level optimization of the transceivers is carried out, and circuit techniques are proposed to reduce the receiver power consumption. To reduce the energy consumption of a duty cycled wireless sensor network transceiver, an optimization method is proposed combining fundamental system relations. The method leads to the optimum choice of noise figure and data rate for a given application and transceiver architecture. Considering a set of typical transceiver parameters, it is shown that the energy consumption can indeed be reduced with about 30% or more with this approach compared to the existing approached of choosing either data rate or noise figure. Moreover, this method is also proven to be effective to reduce energy of a transceiver system with a duty-cycled wakeup receiver.In most transceiver architectures, quadrature generating frequency dividers consume a significant part of the total power. To reduce divider power consumption, still maintaining low output jitter, flipflops for the divider have to be chosen appropriately. An analytic comparison is performed between two types of flipflops, the dynamic transmission gate logic, i.e DTGL and current mode logic i.e. CML. Comparison show that the DTGL flipflop is better for the targeted frequency range in the 90 nm CMOS process, and its benefit increases with reduction of technology feature size. To improve the interference robustness, a chirped-LO based spread spectrum modulation scheme is proposed for FSK and PSK transceiver systems. Chirped-LO based spread spectrum scheme has a potential of ultra low power consumption with simple receiver architecture compared to other spread spectrum schemes. An analysis of the chirped-LO system show that the bit error ratio (BER) of the chirped-LO systems is better than the corresponding non-chirped system when the interference frequency is close to the carrier frequency. The interference robustness of the chirped-LO system is independent of the interference frequency location. Simulation results confirm this analysis. A BER analysis of a chirped-LO direct conversion FSK receiver shows that the in-band interference robustness, i.e. the interference to signal ratio (ISR), can be increased by using a higher chirp bandwidth and a low number of data bits in one chirp. A novel 3-phase direct conversion receiver architecture along with a low power demodulator is designed to reduce receiver energy consumption. The proposed receiver, fabricated in 65 nm CMOS technology, is able to achieve a datarate of 8 Mbps and a sensitivity of -70 dBm at BER of 103, consuming only 219 mW of continuous power from a 1.2 V power supply operating at a RF frequency of 2.45 GHz. Hence it achieves an energy efficiency of 27 pJ/bit, three times better than the previously reported receivers. In the chirped-LO mode, using a chirp spread bandwidth of 360 MHz, the receiver can achieve a 103 BER at an interference to signal ratio of 8 dB across the whole frequency range with only 15 mW of extra power dissipation and a sensitivity degradation of less than 4 dB. This interference robustness is 13.5 dB higher than previously reported interference robustness of ultra low power/energy receivers when the results were published.The ultra low energy techniques that are proposed and proven here can be incorporated in WSNs radios to significantly improve the battery life time of a sensor node. The interferencerobustness technique proposed can be used to improve the robustness of a wirelesssensor network operating with other communication standards.
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