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27074 CSDFa: a model for exploiting the trade-off between data and pipeline parallelism
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Koek, P. and Geuns, S.J. and Hausmans, J.P.H.M. and Corporaal, H. and Bekooij, M.J.G. (2016) CSDFa: a model for exploiting the trade-off between data and pipeline parallelism. In: Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 12-14 jun 2016, St Goar. pp. 30-39. ACM. ISBN 978-1-4503-4320-6

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Real-time stream processing applications, such as SDR applications, are often executed concurrently on multiprocessor systems. A unified data flow model and analysis method have been proposed that can be used to simultaneously determine the amount of pipeline and coarse-grained data parallelism required to meet the temporal constraints of such applications. However, this unified model is only defined for SDF graphs. Defining a unified model for a more expressive model such as CSDF is not possible, because auto-concurrency can cause a time-dependent order of tokens and dependencies.

This paper introduces the CSDFa model. In CSDFa, tokens have indices and the consumption order of tokens is static and time-independent. This allows expressing and trading off pipeline and coarse-grained data parallelism in a single, unified model. Furthermore, we introduce a new type of circular buffer that implements the same static order as is used by the CSDFa model. The overhead of operations on this buffer is independent of the amount of auto-concurrency, which corresponds to the constant firing durations in the CSDFa model.

Exploiting the trade-off between data and pipeline parallelism with the CSDFa model is demonstrated with a part of a FMCW radar processing pipeline. We show that the CSDFa model enables optimizing the balance between processing units and memory, resulting in a significant reduction of silicon area. Additionally, it is shown that reducing the maximum allowed latency increases the minimum required amount of data parallelism by up to a factor of 16.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-General
Research Project:ASSUME: Affordable Safe & Secure Mobility Evolution
Uncontrolled Keywords:Timed-dataflow analysis model
ID Code:27074
Deposited On:13 July 2016
More Information:statisticsmetis

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