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26295 New drain current model for nano-meter MOS transistors on-chip threshold voltage test
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Wan, Jinbo and Kerkhoff, H.G. (2015) New drain current model for nano-meter MOS transistors on-chip threshold voltage test. In: 20th IEEE European Test Symposium, ETS 2015, 25-29 May 2015, Cluj-Napoca, Romania. pp. 1-6. IEEE Computer Society. ISBN 978-1-4799-7603-4

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Traditional reliability tests use complicated equipment, like probe stations and semiconductor parameter analyzers, to measure changes in transistors' threshold voltages, which are both expensive and time consuming. This paper provides an idea to test the threshold voltage with existing low-to-moderate accuracy ADCs and DACs inside SoCs. To avoid the low-accuracy limitation of measurement results, a new MOS model for the nano-meter MOS transistor drain current is proposed. This model only uses six parameters and is valid for all regimes, being the sub-threshold/weak-inversion, moderate-inversion, strong-inversion and linear regime. Measurement results from 90nm transistors and simulation results from 65nm BSIM4.6 models are used to validate the new model. Finally, an on-chip threshold test for reliability purpose is proposed and long-time stress measurement for 90nm PMOS transistors are shown.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-General
Research Project:ELESIS: European Library Based Flow Of Embedded Silicon Test Instruments
ID Code:26295
Deposited On:02 November 2015
More Information:statisticsmetis

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