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26124 Deriving stencil hardware accelerators from a single higher-order function
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Wester, R. and Kuper, J. (2014) Deriving stencil hardware accelerators from a single higher-order function. In: Communicating Processes Architectures 2014, 24-27 Aug 2014, UK. pp. 205-218. Open Channel publishing. ISBN 978-0-9565409-8-0

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Abstract

Stencil computations are array based algorithms that apply a computation
to all array elements in a fixed regular pattern and can be found in many scientific and
engineering applications. Parallelization of these applications becomes more and more
important in order to keep up with the demand for computing power. FPGAs offer a
lot of computing power but are considered hard to program. In this paper, a design methodology based on transformations of higher-order functions is introduced to facilitate this parallelization process. Using this methodology, efficient FPGA hardware is derived achieving good performance. Two architectures for heat flow computations are synthesized for an FPGA and evaluated. To show the general applicability of the design methodology, several applications have been implemented.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-WiSe: Wireless and Sensor Systems
Research Project:CPS-CD: Robust design of cyber-physical systems
Uncontrolled Keywords:stencil computations, space/time tradeoff, Haskell, higher-order function
ID Code:26124
Status:Published
Deposited On:09 July 2015
Refereed:Yes
International:Yes
More Information:statisticsmetis

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