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25452 On the interplay between global DVFS and scheduling tasks with precedence constraints
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Gerards, M.E.T. and Hurink, J.L. and Kuper, J. (2015) On the interplay between global DVFS and scheduling tasks with precedence constraints. IEEE transactions on computers, 64 (6). pp. 1742-1754. ISSN 0018-9340 *** ISI Impact 1,723 ***

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Official URL: http://dx.doi.org/10.1109/TC.2014.2345410

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Abstract

Many multicore processors are capable of decreasing the voltage and clock frequency to save energy at the cost of an increased delay. While a large part of the theory oriented literature focuses on local dynamic voltage and frequency scaling (local DVFS), where every core’s voltage and clock frequency can be set separately, this article presents an in-depth theoretical study of the more commonly available global DVFS that makes such changes for the entire chip. This article shows how to choose the optimal clock frequencies that minimize the energy for global DVFS, and it discusses the relationship between scheduling and optimal global DVFS. Formulas are given to find this optimum under time constraints, including proofs thereof. The problem of simultaneously choosing clock frequencies and a schedule that together minimize the energy consumption is discussed, and based on this a scheduling criterion is derived that implicitly assigns frequencies and minimizes energy consumption. Furthermore, this article studies the effectivity of a large class of scheduling algorithms with regard to the derived criterion, and a bound on the maximal relative deviation is given. Simulations show that with our techniques an energy reduction of 30% can be achieved with respect to state-of-the-art research.

Item Type:Article
Research Group:EWI-CAES: Computer Architecture for Embedded Systems, EWI-DMMP: Discrete Mathematics and Mathematical Programming
Research Program:CTIT-General
Research Project:EASY: Embedded Adaptive Streaming sYstems
Uncontrolled Keywords:Convex programming, Energy aware-systems, Global Optimization, Heuristic methods, Multi-core/single-chip multiprocessors, Scheduling
ID Code:25452
Status:Published
Deposited On:15 December 2014
Refereed:Yes
International:Yes
ISI Impact Factor:1,723
More Information:statisticsmetis

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