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25364 Unified dataflow model for the analysis of data and pipeline parallelism, and buffer sizing
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Hausmans, J.P.H.M. and Geuns, S.J. and Wiggers, M.H. and Bekooij, M.J.G. (2014) Unified dataflow model for the analysis of data and pipeline parallelism, and buffer sizing. In: Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2014, 19-21 Oct 2014, Lausanne, Switzerland. pp. 12-21. IEEE Computer Society. ISBN 978-1-4799-5338-7

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Official URL: http://dx.doi.org/10.1109/MEMCOD.2014.6961839

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Abstract

Real-time stream processing applications such as software defined radios are usually executed concurrently on multiprocessor systems. Exploiting coarse-grained data parallelism by duplicating tasks is often required, besides pipeline parallelism, to meet the temporal constraints of the applications. However, no unified model and analysis method exists that can be used to determine the required amount of data and pipeline parallelism, and buffer sizes simultaneously.

This paper presents an analysis method which can determine the required amount of data parallelism by describing data parallelism in a dataflow model without replicating dataflow actors. This allows to make a trade-off between the amount of data and pipeline parallelism that is required to meet the temporal constraints of the application. It is also shown how large the buffers need to be such that the determined amount of data and pipeline parallelism required for the satisfaction of the throughput constraint, can be realized. Furthermore, it is shown that the use of the applied circular buffers enables the proposed dataflow modeling.

The presented analysis method is demonstrated using a WLAN 802.11p transceiver application. This application contains multi-rate behavior and has a cyclic data dependency because of a re-encoding loop. Given the real-time constraints of the application, sufficient buffer sizes and sufficient data parallelism are derived.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-DSN: Dependable Systems and Networks
Research Project:STARS: Sensor Technology Applied in Reconfigurable systems for Sustainable Security, NEST: Netherlands Streaming Reconfigurable digital antenna processor
ID Code:25364
Status:Published
Deposited On:01 December 2014
Refereed:Yes
International:Yes
More Information:statisticsmetis

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