Dekens, B.H.J. and Wilmanns, P. and Bekooij, M.J.G. and Smit, G.J.M.
Low-cost Guaranteed-Throughput dual-ring communication infrastructure for heterogeneous MPSoCs.
In: 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), 8-10 Oct 2014, Madrid, Spain.
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Official URL: http://dx.doi.org/10.1109/DASIP.2014.7115628
Connection-oriented Guaranteed-Throughput (GT) mesh-based Networks on Chip (NoCs) have been proposed as a replacement for buses in real-time stream processing systems but are currently rarely used as hardware cost tends to be higher than conventional interconnects. Recently an interconnect with a ring topology was introduced as a low-cost alternative for use in medium scale homogeneous Multiple Processor System on Chip (MPSoC) designs. Cost-effective integration of stream processing accelerators would require an extension of this ring interconnect.
We present a dual-ring communication infrastructure for heterogeneous MPSoC designs. Data and credits are transferred between tiles using their separate, oppositely directed, rings. The minimum throughput is determined by analysis of a Cyclo-Static Data Flow (CSDF) model for a system with communication between accelerators and processors.
The performance benefits and costs are evaluated by integration of our dual ring and an accelerator in a 16 core MPSoC which is mapped on a Virtex6 FPGA. On this MPSoC a real-time PAL video decoder is executed. A performance gain of a factor 3.6 was obtained at an increase in hardware cost of only 8.5%.
|Item Type:||Conference or Workshop Paper (Full Paper, Talk)|
|Research Group:||EWI-CAES: Computer Architecture for Embedded Systems|
|Research Program:||CTIT-WiSe: Wireless and Sensor Systems|
|Research Project:||COMMIT/SENSA: Sensor Networks for Public Safety, Vaudeo: Creating intelligent sensor nodes by merging high resolution cameras & acoustic vector sensors providing better situational awareness by capturing more data whilst reporting less data|
|Uncontrolled Keywords:||real-time systems, accelerators, hardware, embedded systems, interconnects|
|Deposited On:||18 December 2014|
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