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25170 Two soft-error mitigation techniques for functional units of DSP processors
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Rohani, A. and Kerkhoff, H.G. (2014) Two soft-error mitigation techniques for functional units of DSP processors. In: 19th IEEE European Test Symposium, ETS 2014 , 28-30 May 2014, Paderborn, Germany. pp. 1-6. IEEE Computer Society. ISBN 978-1-4799-3415-7

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Official URL: http://dx.doi.org/10.1109/ETS.2014.6847792

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Abstract

This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-DSN: Dependable Systems and Networks, CTIT-WiSe: Wireless and Sensor Systems
Research Project:ELESIS: European Library Based Flow Of Embedded Silicon Test Instruments
ID Code:25170
Status:Published
Deposited On:02 December 2014
Refereed:Yes
International:Yes
More Information:statisticsmetis

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