Geuns, S.J. and Hausmans, J.P.H.M. and Bekooij, M.J.G.
Hierarchical programming language for modal multi-rate real-time stream processing applications.
In: Proceedings of the 43rd International Conference on Parallel Processing Workshops (ICPPW 2014), 9-12 Sep 2014, Minneapolis, MN, USA.
IEEE Computer Society.
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Official URL: http://dx.doi.org/10.1109/ICPP.Workshops.2014.66
Modal multi-rate stream processing applications with real-time constraints which are executed on multi-core embedded systems often cannot be conveniently specified using current programming languages. An important issue is that sequential programming languages do not allow for convenient programming of multi-rate behavior, whereas parallel programming languages are insufficiently analyzable such that deadlock-freedom and a sufficient throughput cannot be guaranteed.
In this paper a programming language is proposed by which a sequential specification of the behavior of an application can be nested in a concurrent specification. Multi-rate behavior can be conveniently expressed using concurrent modules which have well-defined, but restricted interfaces. Complex control behavior can be expressed in the sequential specification of the body of a module. The language is not Turing complete such that a Compositional Temporal Analysis (CTA) model can be derived. It is shown that the CTA model can be used despite the presence of control statements and that the composition of black-box components is possible. Algorithms with a polynomial time complexity can be used to verify whether throughput and latency constraints are met and to determine sufficient buffer capacities.
A Phase Alternating Line (PAL) video decoder application is used to demonstrate the applicability of the presented language and analysis approach.
|Item Type:||Conference or Workshop Paper (Full Paper, Talk)|
|Research Group:||EWI-CAES: Computer Architecture for Embedded Systems|
|Research Program:||CTIT-DSN: Dependable Systems and Networks|
|Research Project:||NEST: Netherlands Streaming Reconfigurable digital antenna processor|
|Deposited On:||05 February 2015|
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