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24962 Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs
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Khan, M.A. and Kerkhoff, H.G. (2014) Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. In: 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, 23-25 April 2014, Warsaw, Poland. pp. 15-20. IEEE . ISBN 978-1-4799-4558-0

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In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. The simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-DSN: Dependable Systems and Networks, CTIT-WiSe: Wireless and Sensor Systems
Research Project:ELESIS: European Library Based Flow Of Embedded Silicon Test Instruments
Uncontrolled Keywords:degradation modelling analysis; charge-redistribution SAR ADC; sensitivity analysis; DAC capacitor-array degradation; dependable design
ID Code:24962
Deposited On:28 August 2014
More Information:statisticsmetis

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