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24785 Temporal analysis flow based on an enabling rate characterization for multi-rate applications executed on MPSoCs with non-starvation-free schedulers
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Hausmans, J.P.H.M. and Geuns, S.J. and Wiggers, M.H. and Bekooij, M.J.G. (2014) Temporal analysis flow based on an enabling rate characterization for multi-rate applications executed on MPSoCs with non-starvation-free schedulers. In: Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2014, 10-11 June 2014, St. Goar, Germany. pp. 108-117. ACM. ISBN 978-1-4503-2941-5

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Official URL: http://dx.doi.org/10.1145/2609248.2609262

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Abstract

Real-time stream processing applications often contain multi-rate behavior. This multi-rate behavior can be accurately modeled using Synchronous Dataflow (SDF) graphs. However, no temporal analysis technique exists which is applicable for arbitrary cyclic SDF graphs and can handle cyclic resource dependencies.

This paper presents a temporal analysis flow for SDF graphs which is applicable for systems with non-starvation-free schedulers such as static priority pre-emptive schedulers. The analysis flow uses an enabling rate characterization to calculate response times. This enabling rate characterization is determined using multi-dimensional periodic schedules and allows a more accurate modeling of enabling patterns than is possible with a characterization that is based on periods and enabling jitters.

The presented approach is applicable for arbitrary (cyclic) graph topologies and can take buffer capacity constraints into account during analysis. Also cyclic resource dependencies can be analyzed. The presented analysis flow is the first approach that considers arbitrary SDF graph topologies in combination with cyclic resource dependencies that are caused by non-starvation-free schedulers.

The proposed analysis flow is evaluated using a radio processing application. The analysis results are obtained using a tool in which the analysis flow is implemented. This case-study illustrates that the used enabling characterization achieves up to 87% better response times than with an enabling jitter based characterization.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-DSN: Dependable Systems and Networks
Research Project:NEST: Netherlands Streaming Reconfigurable digital antenna processor
ID Code:24785
Status:Published
Deposited On:30 June 2014
Refereed:Yes
International:Yes
More Information:statisticsmetis

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