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23535 Dataflow Analysis for Multiprocessor Systems with Non-Starvation-Free Schedulers
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Hausmans, J.P.H.M. and Geuns, S.J. and Wiggers, M.H. and Bekooij, M.J.G. (2013) Dataflow Analysis for Multiprocessor Systems with Non-Starvation-Free Schedulers. In: Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, 19-21 June 2013, St. Goar, Germany. pp. 13-22. ACM. ISBN 978-1-4503-2142-6

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Dataflow analysis techniques are suitable for the temporal analysis of real-time stream processing applications. However, the applicability of these models is currently limited to systems with starvation-free schedulers, such as Time-Division Multiplexing (TDM) schedulers. Removal of this limitation would broaden the application domain of dataflow analysis techniques significantly.

In this paper we present a temporal analysis technique for Homogeneous Synchronous Dataflow (HSDF) graphs, that is also applicable for systems with non-starvation-free schedulers. Unlike existing dataflow analysis techniques, the proposed analysis technique makes use of an enabling-jitter characterization and iterative fixed-point computation.

The presented approach is applicable for arbitrary (cyclic) graph topologies. Buffer capacity constraints are taken into account during the analysis and sufficient buffer capacities can be determined afterwards. The approach presented in this paper is the first approach that considers non-starvation-free schedulers in combination with arbitrary HSDF graphs.

The proposed dataflow analysis technique is implemented in a tool. This tool is used to evaluate the analysis technique using examples that illustrate some important differences with other temporal analysis methods. The case-study discusses how the method presented in this paper can be used to solve a problem with the inaccuracy of the temporal analysis results of a real-time stream processing system. This stream processing system consists of an FM receiver together with a DAB receiver application which both share a Digital Signal Processor (DSP).

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-DSN: Dependable Systems and Networks
Research Project:NEST: Netherlands Streaming Reconfigurable digital antenna processor
ID Code:23535
Deposited On:30 July 2013
More Information:statisticsmetis

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