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18437 Boosting Multi-Core Reachability Performance with Shared Hash Tables
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Laarman, A.W. and van de Pol, J.C. and Weber, Michael (2010) Boosting Multi-Core Reachability Performance with Shared Hash Tables. In: Proceedings of the 10th International Conference on Formal Methods in Computer-Aided Design, 20 Oct - 23 Oct 2010, Lugano, Switzerland. pp. 247-256. IEEE Computer Society. ISBN 978-1-4577-0734-6

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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5770956

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Abstract

This paper focuses on data structures for multi-core reachability, which is a key component in model checking algorithms and other verification methods. A cornerstone of an efficient solution is the storage of visited states. In related work, static partitioning of the state space was combined with thread-local storage. This solution leaves room for improvements. This paper presents a solution with a shared state storage. It is based on a lockless hash table implementation and exhibits excellent scalability. The solution is specifically designed for the cache architecture of modern processors. Since model checking algorithms impose loose requirements on the hash table operations, their design can be streamlined substantially compared to related work on hash tables. The resulting speedups are analyzed and compared with related tools. Our implementation outperforms two state-of-the-art multi-core model checkers, SPIN (first presented at FMCAD 2006) and DiVinE, by a substantial margin while placing fewer constraints on the load balancing and search algorithms.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-FMT: Formal Methods and Tools
Research Program:CTIT-DSN: Dependable Systems and Networks
Research Project:CEDICT: 3TU Center of Excellence for ICT
Uncontrolled Keywords:model checking, multi-core, parallel, lockless, hash tables
ID Code:18437
Status:Published
Deposited On:10 January 2011
Refereed:Yes
International:Yes
More Information:statisticsmetis

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