Xing, Jian Sheng and Theelen, B.D. and Langerak, R. and van de Pol, J.C. and Tretmans, G.J. and Voeten, J.P.M.
UPPAAL in Practice: Quantitative Verication of a RapidIO Network.
In: ISoLA 2010 - 4th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation, 18-20 Oct 2010, Amirandes, Heraclion, Crete.
Lecture Notes in Computer Science 6416.
Full text available as:
Official URL: http://dx.doi.org/10.1007/978-3-642-16561-0_20
Packet switched networks are widely used for interconnect-
ing distributed computing platforms. RapidIO (Rapid Input/Output) is an industry standard for packet switched networks to interconnect multiple processor boards. Key performance metrics for these platforms include average-case and worst-case packet transfer latencies. We focus
on verifying such quantitative properties for a RapidIO based multi-processor platform that executes a motion control application. A performance model is available in the Parallel Object-Oriented Specication Language (POOSL) that allows for simulation based estimation results.
It is however required to determine the exact worst-case latency as the application is time-critical. A model checking approach has been proposed in our previous work which transforms the POOSL model into an UPPAAL model. However, such an approach only works for a fairly small
system. We extend the transformation approach with various heuristics to reduce the underlying state space, thereby providing an eective approximation approach that scales to industrial problems of a reasonable complexity.
|Item Type:||Conference or Workshop Paper (Full Paper, Talk)|
|Research Group:||EWI-FMT: Formal Methods and Tools|
|Research Program:||CTIT-DSN: Dependable Systems and Networks|
|Research Project:||Quasimodo: Quantitative System Properties in Model-Driven-Design of Embedded Systems|
|Uncontrolled Keywords:||UPPAAL; POOSL; transformation; quantitative verification; heuristic
|Deposited On:||23 August 2010|
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