EEMCS

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Official URL: http://dx.doi.org/10.1145/1455229.1455231

Abstract

A growing number of applications, often with firm or soft real-time requirements, are integrated
on the same System on Chip, in the form of either hardware or software intellectual property. The
applications are started and stopped at run time, creating different use-cases. Resources, such as
interconnects and memories, are shared between different applications, both within and between
use-cases, to reduce silicon cost and power consumption.
The functional and temporal behaviour of the applications is verified by simulation and formal
methods. Traditionally, designers resort to monolithic verification of the system as whole, since the
applications interfere in shared resources, and thus affect each other’s behaviour. Due to interference
between applications, the integration and verification complexity grows exponentially in the
number of applications, and the task to verify correct behaviour of concurrent applications is on
the system designer rather than the application designers.
In this work, we propose a Composable and Predictable Multi-Processor System on Chip (CoMPSoC)
platform template. This scalable hardware and software template removes all interference
between applications through resource reservations. We demonstrate how this enables a divideand-
conquer design strategy, where all applications, potentially using different programming models
and communication paradigms, are developed and verified independently of one another. Performance
is analyzed per application, using state-of-the-art dataflow techniques or simulation,
depending on the requirements of the application. These results still apply when the applications
are integrated onto the platform, thus separating system-level design and application design.

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