Gerards, M.E.T. and Kuper, J. and Kokkeler, A.B.J. and Molenkamp, E.
Streaming Reduction Circuit.
In: Proceedings of the 12th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, 27-29 Aug 2009, Patras, Greece.
IEEE Computer Society.
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Official URL: http://dx.doi.org/10.1109/DSD.2009.141
Reduction circuits are used to reduce rows of ﬂoating point values to single values. Binary ﬂoating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced.
We present an algorithm by which any number of consecutive rows of arbitrary lengths can be reduced by a pipelined commutative and associative binary operator in an efficient manner. The algorithm is simple to implement, has a low
latency, produces results in-order, and requires only small buffers. Besides, it uses only a single pipeline for the involved operation.
The complexity of the algorithm depends on the depth of
the pipeline, not on the length of the input rows. In this paper we discuss an implementation of this algorithm and we prove its correctness.
|Item Type:||Conference or Workshop Paper (Full Paper, Talk)|
|Research Group:||EWI-CAES: Computer Architecture for Embedded Systems|
|Research Program:||CTIT-WiSe: Wireless and Sensor Systems|
|Research Project:||EASY: Embedded Adaptive Streaming sYstems|
|Deposited On:||11 January 2010|
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