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1530 Mapping the SISO module of the Turbo Decoder to a FPFA
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Smit, G.J.M. and Heysters, P.M. and Havinga, P.J.M. and Smit, L.T. and Smit, J. and Dilessen, J. (2000) Mapping the SISO module of the Turbo Decoder to a FPFA. In: Proceedings of Second international symposium on Mobile Multimedia Systems & Applications (MMSA2000). pp. 165-172.

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Abstract

In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA.

Item Type:Conference or Workshop Paper (Proceedings UNSPECIFIED, Presentation Type UNSPECIFIED)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-UBRICKS: Building Blocks for Ubiquitous Computing and Communication
Additional Information:Imported from CHAMELEON.xml
ID Code:1530
Status:Published
Deposited On:17 February 2006
Refereed:Yes
International:Yes
More Information:statistics

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