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1476 Energy-Efficient NoC for Best-Effort Communication
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Wolkotte, P.T. and Smit, G.J.M. and Becker, J.E. (2005) Energy-Efficient NoC for Best-Effort Communication. In: Proceedings of the 15th International Conference on Field Programmable Logic and Applications 2005 (FPL 2005), 24-26 Aug 2005, Tampere, Finland. pp. 197-202. IEEE Circuits and Systems Society. ISBN 0-7803-9362-7

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Official URL: http://dx.doi.org/10.1109/FPL.2005.1515722

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Abstract

A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture forMulti-Processor System-on-Chip (MPSoC) architectures. In an earlier paper we proposed a energy-efficient reconfigurable circuit-switched NoC to reduce the energy consumption compared to a packetswitched NoC. In this paper we investigate a chordal slotted ring and a bus architecture that can be used to handle the best-effort traffic in the system and configure the circuitswitched network. Both architectures are compared on their latency behavior and power consumption. At the same clock frequency, the chordal ring has the major benefit of a lower latency and higher throughput. But the bus has a lower overall power consumption at the same frequency. However, if we tune the frequency of the network to meet the throughput requirements of control network, we see that the ring consumes less energy per transported bit.

Item Type:Conference or Workshop Paper (Proceedings UNSPECIFIED, Presentation Type UNSPECIFIED)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-UBRICKS: Building Blocks for Ubiquitous Computing and Communication
Research Project:4S: Smart Chips for Smart Surroundings
Additional Information:Imported from CHAMELEON.xml
ID Code:1476
Status:Published
Deposited On:20 February 2006
Refereed:Yes
International:Yes
More Information:statisticsmetis

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