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Wolkotte, P.T. and Smit, G.J.M. and Kavaldjiev, N.K. and Becker, J.E. and Becker, J. (2005) Energy Model of Networks-on-Chip and a Bus. In: Proceedings of the International Symposium on System-on-Chip (SoC 2005), 14-17 Nov 2005, Tampere, Finland. pp. 82-85. IEEE Computer Society. ISBN 0-7803-9294-9
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Official URL: http://dx.doi.org/10.1109/ISSOC.2005.1595650
A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.
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