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Gruian, F. and Westmijze, M.
(2008)
VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.
In: SAC '08: Proceedings of the 2008 ACM symposium on Applied computing, Apr 2008, Fortaleza, Brazil.
pp. 1492-1497.
ACM.
ISBN 978-1-59593-753-7
Full text available as:
Official URL: http://doi.acm.org/10.1145/1363686.1364037  AbstractThis paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Blue-spec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.
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