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12954 Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking

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Barnat, J. and Brim, L. and Šimeček, P. and Weber, Michael (2008) Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking. In: 14th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2008, 29 Mar - 06 Apr 2008, Budapest, Hungary. pp. 48-62. Lecture Notes in Computer Science 4963. Springer Verlag. ISBN 978-3-540-78799-0

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Official URL: http://dx.doi.org/10.1007/978-3-540-78800-3_5

Abstract

Revisiting resistant graph algorithms are those that can tolerate
re-exploration of edges without yielding incorrect results.
Revisiting resistant I/O efficient graph algorithms exhibit
considerable speed-up in practice in comparison to non-revisiting
resistant algorithms. In the paper we present a new revisiting
resistant I/O efficient LTL model checking algorithm. We analyze
its theoretical I/O complexity and we experimentally compare its
performance to already existing I/O efficient LTL model checking
algorithms.

Item Type:	Conference or Workshop Paper (Full Paper, Talk)
Research Group:	EWI-FMT: Formal Methods and Tools
Research Program:	CTIT-DSN: Dependable Systems and Networks
Research Project:	veriGEM: A Verification Grid for Enhanced Model Checking
ID Code:	12954
Status:	Published
Deposited On:	30 June 2008
Refereed:	Yes
International:	Yes
More Information:	statistics metis

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