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12793 Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
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Hansson, A. and Wiggers, M.H. and Moonen, A.J.M. and Goossens, K.G.W. and Bekooij, M.J.G. (2008) Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. In: Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS), 7-10 April 2008, Newcastle upon Tyne. pp. 211-212. IEEE Computer Society. ISBN 0-7695-3098-2

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Official URL: http://dx.doi.org/10.1109/NOCS.2008.4492742

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Abstract

A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.

Item Type:Conference or Workshop Paper (Extended Abstract, Poster)
Research Group:EWI-CAES: Computer Architecture for Embedded Systems
Research Program:CTIT-DSN: Dependable Systems and Networks
Research Project:PASTA: modelling PArallel Systems for Timing Analysis
ID Code:12793
Status:Published
Deposited On:20 June 2008
Refereed:Yes
International:Yes
More Information:statisticsmetis

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