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10974 Faster SPDL Model Checking Through Property-Driven State Space Generation
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Kuntz, G.W.M. and Haverkort, B.R.H.M. (2007) Faster SPDL Model Checking Through Property-Driven State Space Generation. In: Proceedings of the Fourth European Performance Engineering Workshop, EPEW 2007, 27-28 Sept 2007, Berlin, Germany. pp. 80-96. Lecture Notes in Computer Science 4748. Springer Verlag. ISBN 978-3-540-75210-3

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Official URL: http://dx.doi.org/10.1007/978-3-540-75211-0_7

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Abstract

In this paper we describe how both, memory and time requirements for stochastic model checking
of SPDL (stochastic propositional dynamic logic) formulae can significantly be reduced.
SPDL is the stochastic extension of the multi-modal program logic PDL.
SPDL provides means to specify path-based properties with or without timing restrictions.
Paths can be characterised by so-called programs, essentially regular expressions, where the executability
can be made dependent on the validity of test formulae.
For model-checking SPDL path formulae it is necessary to build a product transition system (PTS)
between the system model and the program automaton belonging to the path formula that is to
be verified.
In many cases, this PTS can be drastically reduced during the model checking procedure,
as the program restricts the number of potentially satisfying paths.
Therefore, we propose an approach that directly generates the reduced PTS from a given SPA
specification and an SPDL path formula.
The feasibility of this approach is shown through a selection of case studies,
which show enormous state space reductions, at no increase in generation time.

Item Type:Conference or Workshop Paper (Full Paper, Talk)
Research Group:EWI-DACS: Design and Analysis of Communication Systems
Research Program:CTIT-DSN: Dependable Systems and Networks
Research Project:veriGEM: A Verification Grid for Enhanced Model Checking
ID Code:10974
Status:Published
Deposited On:29 August 2007
Refereed:Yes
International:Yes
More Information:statisticsmetis

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