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Gao, X. and Klumperink, E.A.M. and Nauta, B.
(2007)
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers.
In: Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007), 27-30 May 2007, New Orleans, USA.
.
IEEE Press.
ISBN 1-4244-0921-7
Full text available as: Official URL: http://dx.doi.org/10.1109/ISCAS.2007.378767  AbstractAbstract—This paper shows that, for a given power budget, a
shift register based multi-phase clock generator (MPCG)
generates less jitter than a delay-locked loop (DLL) equivalent
when both are realized with current mode logic (CML) circuits
and white noise is assumed. This is due to the factor that the
shift register MPCG has no jitter accumulation from one clock
phase to the other as in the DLL based MPCG. For N-phase
clock generation, the shift register MPCG needs a reference
clock with N times higher frequency and thus requires a VCO
with higher frequency than the DLL counterpart. However, we
can show that this does not lead to additional power
consumption. | Item Type: | Conference or Workshop Paper (Full Paper, Talk) |
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| Research Group: | EWI-ICD: Integrated Circuit Design |
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| Research Program: | CTIT-WiSe: Wireless and Sensor Systems |
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| Research Project: | Innovative CT: Innovative clocking devices |
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| ID Code: | 10893 |
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| Status: | Published |
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| Deposited On: | 22 October 2007 |
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| Refereed: | Yes |
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| International: | Yes |
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| More Information: | statisticsmetis |
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